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Sanity check: Will automated fill back-annotation help?

By James Paris Hey there, custom integrated circuit (IC) design engineers! If you’re knee-deep in the world of IC design,…

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IC designers: let’s talk about shift left strategies

By John Ferguson In the constantly evolving world of electronics, where demands are high for more powerful, efficient, and reliable…

Transistor-level EMIR analysis from custom design tools? It’s all about flexibility!

By Roger Kang How do you run transistor-level electromigration and voltage drop (EMIR) analysis—command line or an interactive invocation GUI?…

Save yourself the time—here’s a way for you to view native block instances from a full-chip context

By Ritu Walia Imagine this: You primarily work on the design of a sub-block of an application-specific layout design, or…

Calibre PERC checks meet Calibre RVE default views: A match made in debugging heaven?

By Neel Natekar As technology node scaling continues, integrated circuit (IC) designers are facing increasing physical verification challenges due, in…

A recap of Calibre at DAC 2023

DAC is back! At least was the feeling on the floor, judging by the number of attendees we talked to,…

Updating a Calibre DesignEnhancer via insertion kit is fast and easy!

By Jimmy Tien The Calibre® DesignEnhancer Via use model provides an automated via insertion process based on foundry design rule…

Optimize metal fill insertion while protecting critical nets and devices…automatically!

By Dina Medhat Context-aware physical verification (PV) is a relatively new addition to traditional PV flows, but it has quickly…

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